04.pdf

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Co zawiera komputer PC ?

c

Technika cyfrowa 2

cc

wykĀad 4

c

Katedra Metrologii Elektronicznej i Fotonicznej

Andrzej Stİpieĺ

A to jest w mikrokontrolerze

MCS

À 51 Family (8 - bit)

ÒC51

ÒC517A

c

Wewnħtrzna pamiħę ROM

Wewnħtrzna

pamiħę RAM

(XDATA)

cc

Wewnħtrzna pamiħę

RAM (DATA, IDATA)

Port

P0

we/wy

we

analo-

gowe/

/cyfro-

we

Port

P7

Port

P8

Licznik

T0

Port

P1

10-bitowy

przetwornik

analogowo-

-cyfrowy

Jednostka

arytmetyczno-

-logiczna

ALU

Port

szeregowy

we/wy

Licznik

T1

Port

P2

we/wy

c

koprocesor

arytmetyczny

Licznik

T2

Port

P3

Port

P5

we/wy

Watchdog

we/wy

Port

P6

Licznik

CT

Port

P4

2 Porty

szeregowe

we/wy

we/wy

Generator + redukcja mocy

ST7 Family (8-bit, STMicroelectronics)

MSP430F13x/14x Mixed Signal Microcontroller (16 - bit)

c

c

mcu.st.com/mcu/modules

Documents and files for family ST7.

ST7 Training Î Core: 1117550082.pdf (1,322MB)

1

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AT9 1 SAM7x x - AT91 A RM Thumb Device (Atmel W&M)

Cechy mikrokontrolera

JTAG Scan

ARM7TDMI

Processor

32-bit

Bus

Voltage

Regulator

Advanced Int Ctrl

Wewnħtrzna pamiħę programu

(ROM, OTPROM, EPROM, FLASH)

Priorytetowy kontroler przerwaı

(wewnħtrzne / zewnħtrzne,

maskowalne / niemaskowalne)

Przetworniki A/C i C/A

(rozdzielczoĻę: 8 .. 24 bity)

Liczniki (8 .. 32-bitowe,

tryby: Compare, Capture,

Reload, PWM ..)

Porty rwnolegþe

Porty szeregowe (UART,

standard: I 2 C-Bus / SMBus, SPI,

1-Wire, MicroWire,

USB, CAN ..)

Power Mgt Ctrl

PLL

Osc RSOsc

Reset Ctrl

BrownOut Dtr

Power On Reset

SRAM

Peripheral

Bridge

Wewnħtrzna pamiħę danych

(RAM, EEPROM)

Wewnħtrzny/zewnħtrzny generator

(rezonator kwarcowy/ceramiczny

ukþad RC/LC)

Flash

32-bit

Bus

MCU

WDT

RTC

Peripheral

Data Ctrl

Flash

Programmer

Prog Int Timer

Debug Unit

PIO Ctrl

Power Fail / Brown Out Detect

USART 0-1

SPI

USB Device

PWM Ctrl

Napiħcie zasilania Vcc = 1,2 .. 6V

PrĢd zasilania Icc = 10

mA .. 30mA

Two Wire Interface

Synchro Serial Ctrl

Tryby redukcji mocy

(Idle, Halt, SlowDown, PowerDown, PPM ..

ADC0-7

Timer/Counter 0-2

CPU Architecture (1/2)

mC Introduction

C515

ST72334

63 basic instructions

Fast 8-bit by 8-bit multiply

17 main addressing modes

One 8-bit accumulator A

One 8-bit condition code

register CC (using only 5 bits)

Two 8-bit index registers:

X and Y

C515

ST72334

von Neumann Architecture

Harward Architecture

111 basic instructions

Fast 8-bit by 8-bit multiply / divide

5 main addressing modes

One 8-bit accumulator A

One 8-bit program status word

PSW (using 8 bits)

Eight 8-bit registers Rn in four

selected banks

Eight 16-bit data pointer register

DPTR

8-bit stack pointer SP

16-bit program counter PC

0000h

Hardware

Register

007Fh

0080h

Data Memory

RAM (512 Bytes )

Core

027Fh

External

/

Internal

Program

Memory

(max 64KB )

Core

Reserved

External

Data

Memory

(max 64KB )

0C00h

Special

Function

Register

(256 Bytes)

Internal

Data

Memory

(128 Bytes )

Internal

Data

Memory

(128 Bytes )

EEPROM (256 Bytes) 0CFF h

Reserved

C000h

FFDF h

Program Mamory

ROM (16KBytes)

7Fh

16-bit stack pointer SP

16-bit program counter PC

FFE0h

FFFFh

Interrupt &

Reset Vectors

Rn

00h

CPU Architecture (2/2)

CPU Registers - Accumulator A

The accumulator A is the register where the arithmetic and logic

operations are performed. To perform a two-operand operation

between two values stored in memory, one of the values must first be

moved to the accumulator, since the instruction code provides only

one address. It must be moved back to memory or register when the

operation is done.

C515

ST72334

ROM

RAM

SP

SFR

ROM

RAM

SP

Periph

The instructions that require only one operand, like INCrement,

DECrement, ComPLement, ComPare, and so on, can act on the

accumulator, or directly on the data in memory or in special function

register if so desired.

Rn

B

A

temp

X

Y

A

temp

ALU

ALU

DPTR

PSW

CC

Reset value = 00h (for C515)

xxh (ST72334)

PC

PC

addr in SFR: Acc = 0E0h (C51 only)

2

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ST72334 CPU Registers - Index Registers (X and Y)

C515 CPU Registers - Data Pointer Register

The index registers X and Y are meant

to hold addresses, unlike the

accumulator which is meant to hold

data. The value stored in X or Y is

involved in the effective address

calculation in some addressing modes.

The availability of two index registers

(X and Y) allows for calculating and

managing two addresses as is needed

in a memory-to-memory data move,

with or without alteration in between.

However, these registers may also be

used to store temporary data.

Reset value = xxh

ROM

RAM

SP

SFR

ROM

RAM

SP

Periph

8-bit accesses to the internal

XRAM data memory or the

external data memory or the

code memory are executed

using the data pointer DPTR as

an 16-bit address

Rn

B

A

temp

X

Y

A

temp

ALU

DPTR

PSW

ALU

CC

addr in SFR: DPL=82h

DPH=83h

Reset value = 0000h

PC

PC

ST72334 CPU Registers - Condition Code Register (1/2)

ST72334 CPU Registers - Condition Code Register (2/2)

The CC register remembers the

conditions after each instruction, and

these conditions are used by the

conditional jump instructions. The

CC is laid out as follows:

This register holds several bits that

are actually more or less

independent from one another.

These bits are set or reset (or left

unchanged) after the execution of

certain instructions. For example, if

an addition produces a null result,

the Z flag is set; otherwise, it is reset.

If the result is negative, the N flag is

set, otherwise it is reset and so on.

Reset value = 111X 1XXX

ROM

RAM

SP

Periph

ROM

RAM

SP

Periph

X

Y

A

temp

X

Y

A

temp

1

1 1 H

I

N Z C

ALU

ALU

CC

CC

H - Half carry

I - Interrupt mask

N - Negative

Z - Zero

C - Carry/borrow

PC

PC

C515 CPU Registers - Program Status Word Register

Condition Î CY, C

ROM

RAM

SP

SFR

C515

ST72334

Reset value = 00h

C - Carry

AC - Auxiliary Carry

F0 - General purpose user flag 0

RS1,RS0 - Register Bank select

OV - Overflow

F1 - General purpose user flag 1

P - Parity

CY AC F0 RS1 RS0 OV F1 P

1

1 1 H

I

N Z C

Rn

B

A

temp

Carry Flag (CY) Î C515

Used by arithmetic (unsigned) and conditional branch instruction.

ALU

DPTR

PSW

Carry/Borrow (C) Î ST7

When set, C indicates that a carry or borrow out of the ALU occurred

during the last arithmetic operation on the MSB operation result bit.

This bit is also affected during bit test, branch, shift, rotate and load

instructions.

PC

addr in SFR: 0D0h

CY AC F0 RS1 RS0 OV F1 P

3

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Condition Î AC, H

Condition Î OV, P

C515

ST72334

C515

ST72334

CY AC F0 RS1 RS0 OV F1 P

1

1 1 H

I

N Z C

CY AC F0 RS1 RS0 OV F1 P

1

1 1 H

I

N Z C

Auxiliary Carry Flag (AC) Î C515

Used by instructions which execute BCD operations.

Overflow Flag (OV) Î C515

Used by arithmetic instruction (signed).

Half carry bit (H) Î ST7

The H bit is set to 1 when a carry occurs between the bits 3 and 4 of

the ALU during an ADD or ADC instruction. The H bit is useful in BCD

arithmetic subroutines.

Parity Flag (P) Î C515

Always set/cleared by hardware to indicate an odd/even number of

ÐoneÑ bits in the accumulator.

Condition Î I, N, Z

C51 - Addressing Mode (1/2)

C515

ST72334

Immediate Addressing Mode (natychmiastowe):

MOV A, #3

CY AC F0 RS1 RS0 OV F1 P

1

1 1 H

I

N Z C

; A 3, wartoĻę

Interrupt mask (I)

When the I bit is set to 1, all interrupts are disabled. Clearing this bit

enables them. Interrupts requested while I is set, are latched and can be

processed when I is cleared (only one interrupt request per interrupt

enable flag can be latched). This bit can be set/reset by software and is

automatically set after reset or at the beginning of an interrupt routine.

Negative (N)

When set to 1, this bit indicates that the result of the last arithmetic,

logical or data manipulation is negative (i.e. the most significant bit is a

logic 1).

Zero (Z)

When set to 1, this bit indicates that the result of the last arithmetic,

logical or data manipulation is zero.

Register Addressing Mode (rejestrowe):

MOV A, R1

; A R1, nazwa rejestru

Direct Addressing Mode (bezpoĻrednie) :

MOV A, 1

; A (1), adres pamiħci

Indirect Addressing Mode (poĻrednie) :

MOV A, @R1

; A (R1), adres pamiħci w R1

IDATA

(R1)

2Ah

A

C51 - Addressing Mode (2/2)

ST7 - Addressing Mode (1/4)

(http://mcu.st.com/mcu: 1117550405.pdf)

¤ Inherent (wþaĻciwe):

PUSH A

Indirect Register - Indexed Addressing Mode (rejestrowo-

indeksowo-poĻrednie) :

MOVC A, @A+DPTR

; (Stack) A

; A (A+DPTR), adres pamiħci w A+DPTR

¤ Short Direct Addressing Mode (bezpoĻrednie, krtkie) :

INC LABEL

; (LABEL) (LABEL) + 1

; ADDRESSABLE SPACE: 00 to FF

CODE

DPTR+0

¤ Immediate Addressing Mode (natychmiastowe):

LD A, #$55

; A $55

A

4Fh

¤ Long Direct Addressing Mode (bezpoĻrednie dþugie) :

ADD A, LABEL

DPTR+A

; A A + (LABEL)

; ADDRESSABLE SPACE: 0000 to FFFF

4

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ST7 - Addressing Mode (2/4)

ST7 - Addressing Mode (3/4)

$5A

$4C

¤ No Offset Indexed Addressing Mode :

CPL (X) ; (X) NOT (X)

¤ Short Indexed Addressing Mode :

RRC (LABEL, X)

¤ Short Indirect Addressing Mode :

SWAP [LABEL] ; SWAP ((LABEL))

¤ Long Indirect Addressing Mode :

LD A, [LABEL.w] ; A ((LABEL)*256 + (LABEL+1))

¤ Short Indirect Indexed Addressing :

CLR ([LABEL], X) ; ((LABEL) + X) 0

¤ Long Indirect Indexed Addressing :

LD A, ([LABEL.w], X)

; A ((LABEL)*256 + (LABEL+1) + X)

$4C

LABEL

; C (LABEL + X) C

LABEL+0

rotate right logical

through Carry

LABEL+X

$82

$5A

$4C

LABEL+0

LABEL+1

¤ Long Indexed Addressing Mode :

LD X, (LABEL, X)

$5A4C+0

; X (LABEL + X)

A

$5A4C+X

$82

ST7 - Addressing Mode (4/4)

MCS

° 51 na stronach www

¤ www.8052.com

¤ Relative Addressing Mode Î Direct / Indirect Addressable Space

JRMI LABEL or JRMI [LABEL]

; Jump Relative: PC PC + dst if Condition is True (MI = Minus, N=1)

¤ www.atmel.com

¤ www.cygnal.com / www.silabs.com

¤ www.infineon.com

¤ www.intel.com

¤ www.maxim-ic.com

¤ www.semiconductors.philips.com

¤ www.st.com

¤ www.ti.com

¤ Bit Manipulation Î Direct / Indirect Addressable Space

BSET variable, #n

; set bit n in variable

BRES [variable], #n

; clear bit n in (variable)

¤ Relative Jump On BIT Test Î Direct / Indirect Addressable Space

BTJT variable, #n, label

takŇe ST7

mcu.st.com/mcu

; jump to LABEL if bit n in variable

BTJT [variable], #n, label

; jump to LABEL if bit n in (variable)

C51 Î typy pamiħci

C51 Î adresowanie pamiħci danych i kodu

CODE

XDATA

zewnħtrzna

pamiħę

kodu

programu

zewnħtrzna

pamiħę

danych

zewnħtrzna

pamiħę

kodu

programu

zewnħtrzna

pamiħę

danych

adresowanie

poĻrednie

( @Ri, @DPTR )

CODE

XDATA

DATA

IDATA

0FFh

adresowanie

indeksowo-rejestrowo-poĻrednie

( @A+DPTR )

adresowanie

natychmiastowe

( #data )

SFR

RAM

wewnħtrzna

pamiħę

danych

wewnħtrzna

pamiħę

kodu

programu

wewnħtrzna

pamiħę

danych

wewnħtrzna

pamiħę

kodu

programu

80h

7Fh

R A M

IDATA

DATA

rejestry

0

0

0

0

0

5

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